Hierarchical temporal memory (HTM) tries to mimic the computing incerebral-neocortex. It identifies spatial and temporal patterns in the inputfor making inferences. This may require large number of computationallyexpensive tasks like, dot-product evaluations. Nano-devices that can providedirect mapping for such primitives are of great interest. In this work we showthat the computing blocks for HTM can be mapped using low-voltage,fast-switching, magneto-metallic spin-neurons combined with emerging resistivecross-bar network (RCN). Results show possibility of more than 200x lowerenergy as compared to 45nm CMOS ASIC design
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